(1) Field of the Invention
The present invention relates to a phase adjusting circuit for adjusting a phase of each bit of serial data by synchronizing with a system clock, in other words, a phase adjusting circuit for converting data synchronized with a first clock to data synchronized with a second clock.
Generally, a data processing system includes a plurality of sub-units for carrying out various kinds of data processing operations, each of the sub-units in the system usually operates synchronized with one or more clocks, and all the clocks are generated from a common master clock. Data processed in each of the sub-units is, therefore, synchronized with the clock in the sub-unit, but, when data output from one sub-unit is transferred to an other sub-unit, a phase difference occurs between data from the two sub-units due to a delay during the transferring operation or the like.
When data is input into a sub-unit, each bit of the data must be first synchronized with a system clock in the sub-unit for being processed in the sub-unit. As a most typical example, in a data multiplexing apparatus, data from a plurality of units must be multiplexed synchronized with a sending clock.
To synchronize data with the system clock, each bit of input data is read at the timing of a rising or falling edge of the system clock by an edge-triggered operation. Since the value of data in each bit is not necessarily stable near the data changing points (timings), i.e., near the beginning time of or the ending time of the duration of a data value of each bit, the above edge-triggered operation is required to be carried out at the time when the data is stable.
In practice, when designing and constructing a circuit for carrying out the above edge-triggered operation, there is an additional difficulty to determine an accurate timing of the edge-triggered operation, due to a small but significant difference in delays occurring in individual circuits. The difference cannot be eliminated because geometries of the circuit arrangement and characteristics of circuit elements used in individual circuits are inevitably somewhat different from each other. Thus, a variation in the timing of the above edge-triggered operation may cause an error when inputting bit data transferred from an other unit.
(2) Description of the Related Art
In the prior art, to synchronize input data with the system clock, each bit of data is first stored in a memory circuit, e.g., an elastic memory, and is then read out at the timing of the system clock. However, the use of the memory circuit for this purpose increases the cost and the scale of the circuitry, and further slows the operation. Therefore, the applicants previously proposed the following construction of a phase adjusting circuit which reduces the cost and the scale of the circuitry, and further quickens the operation.
FIG. 1 shows the construction of the above-mentioned phase adjusting circuit in the prior art for adjusting a phase of each bit of serial data by synchronizing with a system clock, in other words, a phase adjusting circuit for converting data synchronized with a first clock to data synchronized with a second clock, which was provided by the applicants and is disclosed in the Japanese Unexamined Patent Publication NO. 64-77241.
In FIG. 1, reference numerals 51, 52, 53 and 55 each denote a D-type flip-flop circuit, 56 and 57 each denote a delay circuit, and 54 denotes an exclusive NOR circuit. In addition, CK2 denotes a system clock, D1 denotes input data, CK1 denotes a receiving clock which is extracted from the input data D1, and D2 denotes output data the phase of which has been adjusted by the system clock CK2.
The input data D1 is applied to the data input terminal of the D-type flip-flop circuit 51, and the receiving clock CK1 is applied to the edge-triggered input terminal of the D-type flip-flop circuit 51. Therefore, the D-type flip-flop circuit 51 outputs the input data synchronized with the receiving clock CK1, and then the output is applied to the data input terminal of the D-type flip-flop circuit 55.
The above receiving clock CK1 is also input into the delay circuit 56. The output of the delay circuit 56 is applied to the data input terminal of the D-type flip-flop circuit 53 and to one input terminal of the exclusive NOR circuit 54. On the other hand, the system clock CK2 is applied to the edge-triggered input terminal of the D-type flip-flop circuit 53 through the delay circuit 57. Then, the Q-output of the D-type flip-flop circuit 53 is applied to the other input terminal of the exclusive NOR circuit 54. The output of the exclusive NOR circuit 54 is applied to the edge-triggered input terminal of the D-type flip-flop circuit 55. The Q-output of the D-type flip-flop circuit 55 is applied to the data input terminal of the D-type flip-flop circuit 52. The above system clock CK2 is also applied to the edge-triggered input terminal of the D-type flip-flop circuit 52. Thus, the above-mentioned output data D2 is obtained as the the Q-output of the D-type flip-flop circuit 52.
The D-type flip-flop circuit 51 functions as an input buffer register, the D-type flip-flop circuit 52 functions as an output buffer register, and the Q-output of the D-type flip-flop circuit 51 is input into (i.e., is output from) the D-type flip-flop circuit 55 at an intermediate timing between the receiving clock CK1 and the system clock CK2. The timing of the intermediate timing is controlled as follows.
FIGS. 2A and 2B show timings in the operation of the construction of FIG. 1.
As shown in FIGS. 2A and 2B, the clock CK1 is delayed in the delay circuit 56 so that each duration of a low level state lies in the center of a duration of the output of a data bit (although not shown in FIG. 2A, a high level state instead of the low level, may be in the center of the duration of a data bit).
As shown in FIG. 2A, when the output of the delay circuit 57 (which is a delayed system clock CK2) rises while the level of the delay circuit 56 (which is a delayed receiving clock CK1) is high, the Q-output of the D-type flip-flop circuit 53 is at a high level, and therefore, the output of the delay circuit 57 is applied to the edge-triggered input terminal of the D-type flip-flop circuit 55 through the exclusive NOR circuit 54. Therefore, the Q-output of the D-type flip-flop circuit 51 is input into the D-type flip-flop circuit 55 at the timing of rising edge of the output of the exclusive NOR circuit 54. Next, the Q-output of the D-type flip-flop circuit 55 is input into the D-type flip-flop circuit 52 at the timing of the rising edge of the system clock CK2.
As shown in FIG. 2B, when the output of the delay circuit 57 rises while the level of the delay circuit 56 (which is a delayed receiving clock CK1) is low, the Q-output of the D-type flip-flop circuit 53 is at a low level, and therefore, the output of the delay circuit 57 is inverted in the exclusive NOR circuit 54, and is then applied to the edge-triggered input terminal of the D-type flip-flop circuit 55. The Q-output of the D-type flip-flop circuit 51 is input into the D-type flip-flop circuit 55 at the timing of rising edge of the output of the exclusive NOR circuit 54, i.e., at the timing of falling edge of the output of the delay circuit 56. Next, the Q-output of the D-type flip-flop circuit 55 is input into the D-type flip-flop circuit 52 at the timing of the rising edge of the system clock CK2.
In both cases of FIGS. 2A and 2B, i.e., regardless of the phase of the output of the delay circuit 57 (regardless of the phase of the system clock CK2), the timing at which the Q-output of the D-type flip-flop circuit 54 is input into the D-type flip-flop circuit 52 is limited within the range W. Thus, the aforementioned synchronization of input data with the system clock CK2 by reading each bit of data at the timing of an rising or falling edge of the system clock by an edge-triggered operation, is carried out at the timings rather apart from the data changing points of each bit data. The distances from the above range W of the timing of the edge-triggered operation to the data changing points in both sides of the range W, which are defined as phase margins in the construction of FIG. 1, are denoted by PM1 and PM2 in FIGS. 2A and 2B.
The width of the range w is determined by the duration of the level of the delay circuit 56 is low (or high) shown in FIG. 2A and FIG. 2B, i.e., a phase of 180.degree. (a half cycle of the cycle time of the input data, i.e., a half of the duration of one input data bit).
In a typical example wherein the frequency of the input data is 100MHz, the above phase margins PM1 and PM2 are each 2.5 ns.
However, generally, the duty factor of the input data signal (the ratio of the width of the high level signal in a cycle time to the cycle time) varies around the 50%. For example, when the duty cycle is less than 50%, as shown in FIGS. 2A and 2B, the above phase margins PM1 and PM2 are reduced, i.e., the extent of the above-mentioned timing of the edge-triggered operation can approach the data changing points. As mentioned before, this increases in the possibility of an occurrence of an error in reading data for synchronization with the system clock.
Generally, the relative extent of the vicinity of the data changing point in a cycle wherein the value of the data signal is unstable, and the above possibility of an occurrence of an error resulting from the instability, depend on the frequency of the input signal and the response speeds of the elements constituting the circuit. Higher frequency and lower response speed make the relative extent of the instable region in a cycle time larger, and the possibility of an occurrence of an error higher.